Title:
個別の符号帳情報についての個別の置き換えＬＰＣ表現を用いたエラー隠し信号を生成する装置及び方法
Document Type and Number:
Japanese Patent JP6457061
Kind Code:
B2
Abstract:
An apparatus for generating an error concealment signal, comprises: an LPC (linear prediction coding) representation generator (100) for generating a first replacement LPC representation and a different second replacement LPC representation; an LPC synthesizer (106) for filtering a first codebook information using the first replacement representation to obtain a first replacement signal and for filtering a different second codebook information using the second replacement LPC representation to obtain a second replacement signal; and a replacement signal combiner (110) for combining the first replacement signal and the second replacement signal to obtain the error concealment signal (111).
Inventors:
Schnabel, Michael
Reconte, Jeremy
Spear Schneider, Ralph
Yander, Manuel
Reconte, Jeremy
Spear Schneider, Ralph
Yander, Manuel
Application Number:
JP2017500141A
Publication Date:
January 23, 2019
Filing Date:
March 04, 2015
Export Citation:
Assignee:
Fraunhofer-Gesellschaft Tool Felderung del Angewanten Forsung Eingetler Genel Fehlein
International Classes:
G10L19/005
Domestic Patent References:
| JP2002236495A | ||||
| JP10308708A | ||||
| JP736496A | ||||
| JP2004508597A |
Foreign References:
| WO2008056775A1 | ||||
| WO2012110447A1 |
Other References:
"Frame error robust narrow-band and wideband embedded variable bit-rate coding of speech and audio from 8-32 kbit/s",Recommendation ITU-T G.718,2008年 6月,pp.204-224
Attorney, Agent or Firm:
Hidetaka Tsutsui