Title:
半導体装置
Document Type and Number:
Japanese Patent JP6457670
Kind Code:
B2
Abstract:
By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
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Inventors:
Shunpei Yamazaki
Jun Koyama
Masahiro Takahashi
Hideyuki Kishida
Miyanaga Saki
Suhei Suo
Hideki Uochi
Nakamura Yasuo
Jun Koyama
Masahiro Takahashi
Hideyuki Kishida
Miyanaga Saki
Suhei Suo
Hideki Uochi
Nakamura Yasuo
Application Number:
JP2018015128A
Publication Date:
January 23, 2019
Filing Date:
January 31, 2018
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L29/786; G02F1/1368; G09F9/30; H01L21/28; H01L21/3205; H01L21/768; H01L23/532; H01L27/32; H01L29/417; H01L29/423; H01L29/49; H01L51/50; H05B33/02
Domestic Patent References:
| JP2007165860A | ||||
| JP2005159326A | ||||
| JP10229200A | ||||
| JP2009158940A | ||||
| JP2007123861A | ||||
| JP2005049832A | ||||
| JP2008070876A | ||||
| JP9152625A | ||||
| JP2008124499A | ||||
| JP2009167087A | ||||
| JP2009528670A |
Foreign References:
| US20070111144 | ||||
| US20050095842 | ||||
| US20090140438 |