Title:
電子パッケージ用の電気インターコネクト
Document Type and Number:
Japanese Patent JP6466305
Kind Code:
B2
Abstract:
Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a trench formed into one surface of the dielectric layer and a signal conductor that fills the trench and extends above the one surface of dielectric layer. The electrical interconnect further includes a conductive reference layer mounted on an opposing side of the dielectric layer. The conductive reference layer is electromagnetically coupled to the signal conductor when current passes through the signal conductor.
Inventors:
Can Chun Yong
Bokuen Chair
Theon Caret B
Howard El. Heck
Jackson Chun Phuong Cone
Stephen H. Hall
Kui Chi Woo
Bokuen Chair
Theon Caret B
Howard El. Heck
Jackson Chun Phuong Cone
Stephen H. Hall
Kui Chi Woo
Application Number:
JP2015208684A
Publication Date:
February 06, 2019
Filing Date:
October 23, 2015
Export Citation:
Assignee:
Intel Corporation
International Classes:
H01L23/12; H05K1/02; H05K1/11; H05K3/10; H05K3/18; H05K3/40
Domestic Patent References:
| JP2006093324A | ||||
| JP2001203300A | ||||
| JP2007288180A | ||||
| JP2009038250A | ||||
| JP2012124452A | ||||
| JP6005593A | ||||
| JP2013051367A | ||||
| JP2012227211A | ||||
| JP2001053507A |
Foreign References:
| US20030230807 | ||||
| WO2010064467A1 |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Shinsuke Onuki
Tadahiko Ito
Shinsuke Onuki