Title:
パワーアンプ制御回路
Document Type and Number:
Japanese Patent JP6492062
Kind Code:
B2
Abstract:
Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage.
Inventors:
Arok Prakash Joshi
Gilly Run Legend Run
Gilly Run Legend Run
Application Number:
JP2016515140A
Publication Date:
March 27, 2019
Filing Date:
May 27, 2014
Export Citation:
Assignee:
Texas Instruments Japan Ltd.
Texas Instruments Incorporated
Texas Instruments Incorporated
International Classes:
H03F1/02; H03F3/68
Domestic Patent References:
| JP2008160661A | ||||
| JP2012070267A | ||||
| JP2012070151A |
Foreign References:
| US20090256631 | ||||
| US8212613 | ||||
| US20120112835 | ||||
| FR3015811A1 |
Attorney, Agent or Firm:
Kyozo Katayose