Title:
薄膜電子回路をカスタマイズするための方法
Document Type and Number:
Japanese Patent JP6496742
Kind Code:
B2
Abstract:
Method for customizing thin film electronic circuits A method for manufacturing a thin-film circuit is provided, the method comprising: (a) obtaining a thin-film circuit comprising at least one logic gate circuit having an output, the at least one logic gate circuit comprising a plurality of drive transistors and a plurality of load elements, at least one load element being electrically connected to the output; (b) sequentially providing a series of predetermined voltage patterns to the plurality of drive transistors, a voltage pattern comprising a set of voltages to be applied respectively between a gate and a source of a respective drive transistor; (c) measuring a series of output voltage values of the at least one logic gate circuit corresponding to the series of predetermined voltage patterns; (d) comparing the series of output voltage values with a series of respective predetermined reference output voltage values; (e) in case an output voltage value does not match the respective predetermined reference output voltage value, adapting the number of load elements electrically connected to the output; and (f) repeating steps (b) to (e) until the series of output voltage values matches the series of predetermined reference output voltage values.
Inventors:
Chris Yeh Leah Mini
Helwin Herrink
Yang Henu
Helwin Herrink
Yang Henu
Application Number:
JP2016550217A
Publication Date:
April 03, 2019
Filing Date:
February 11, 2015
Export Citation:
Assignee:
IMEC VZW
International Classes:
G11C17/14
Domestic Patent References:
| JP2007180543A | ||||
| JP2005203763A | ||||
| JP2254700A |
Foreign References:
| WO2006003844A1 |
Attorney, Agent or Firm:
Takuji Yamada
Mitsuo Tanaka
Kawabata Junichi
Mitsuo Tanaka
Kawabata Junichi