Title:
半導体装置及びその製造方法
Document Type and Number:
Japanese Patent JP6519649
Kind Code:
B2
Abstract:
A p-type base layer (2) is formed on a surface of an n-type silicon substrate (1). First and second n+-type buffer layers (8,9) 9 are formed on a back surface of the n-type silicon substrate (1). The first n+-type buffer layer (8) is formed by a plurality of implantations of protons at different accelerating voltages and has a plurality of peak concentrations with different depths from the back surface of the n-type silicon substrate (1). The second n+-type buffer layer (9) is formed by an implantation of a phosphorus. A position of a peak concentration of the phosphorus is shallower from the back surface of the n-type silicon substrate (1) than positions of peak concentrations of the protons. The peak concentration of the phosphorus is higher than the peak concentrations of the protons. A concentration of the protons is higher than a concentration of the phosphorus at the positions of the peak concentrations of the protons.
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Inventors:
Kenji Suzuki
Atsushi Narasaki
Kamibaba Ryu
Fukada Yusuke
Katsumitsu Nakamura
Atsushi Narasaki
Kamibaba Ryu
Fukada Yusuke
Katsumitsu Nakamura
Application Number:
JP2017505779A
Publication Date:
May 29, 2019
Filing Date:
March 13, 2015
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L29/739; H01L21/336; H01L29/78
Domestic Patent References:
| JP4128777B2 | ||||
| JP2013138172A | ||||
| JP2002507058A | ||||
| JP2009176892A | ||||
| JP2009188336A |
Foreign References:
| WO2013073623A1 | ||||
| WO2013147274A1 | ||||
| WO2011052787A1 |
Attorney, Agent or Firm:
Mamoru Takada
Hideki Takahashi
Yoshimi Kuno
Hideki Takahashi
Yoshimi Kuno