Title:
半導体集積回路の試験回路及びこれを用いた試験方法
Document Type and Number:
Japanese Patent JP6530216
Kind Code:
B2
Abstract:
A testing circuit is arranged in a semiconductor integrated circuit so as to detect a delay fault in the semiconductor integrated circuit. The semiconductor integrated circuit includes a first output control circuit having a plurality of sequential circuits, a first combination circuit connected to the first output control circuit, and a memory circuit connected to the first combination circuit. The testing circuit includes the first output control circuit; a second output control circuit; and a third output control circuit. The testing circuit, under control of a testing apparatus connected to the semiconductor integrated circuit, is configured to perform steps to detect the delay fault in the semiconductor integrated circuit.
Inventors:
Hiroyuki Nakamura
Application Number:
JP2015065953A
Publication Date:
June 12, 2019
Filing Date:
March 27, 2015
Export Citation:
Assignee:
Mega Chips Co., Ltd.
International Classes:
G01R31/28; G11C7/00; G11C29/04
Domestic Patent References:
| JP2009205414A | ||||
| JP2006073917A | ||||
| JP2001013220A | ||||
| JP11023660A | ||||
| JP2001004710A |
Foreign References:
| US20120198294 |
Attorney, Agent or Firm:
Hide Tanaka Tetsu
Hideaki Shioya
Hideaki Shioya