Title:
分配されたキャパシティブ遅延追跡ブーストの支援回路
Document Type and Number:
Japanese Patent JP6560965
Kind Code:
B2
Abstract:
According to one general aspect, an apparatus may include a plurality of voltage boosted circuits. Each voltage boosted circuit may include a power gater configured to select between an array supply voltage and a second voltage, wherein the second supply voltage is greater than the array supply voltage. Each voltage boosted circuit may include may also include a distributed boost capacitor configured to generate, in part, the second supply voltage. Each distributed boost capacitor may be physically located throughout a boosting network. Each voltage boosted circuit may further include a driver configured to generate an electrical signal based upon, as selected by the power-gater, either the array supply voltage or the second supply voltage.
Inventors:
Macey Bayakowski
Jean-Michael Hoover
Ravi Bencateza
Jean-Michael Hoover
Ravi Bencateza
Application Number:
JP2015226232A
Publication Date:
August 14, 2019
Filing Date:
November 19, 2015
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C11/4074; H02M3/07
Domestic Patent References:
| JP10337002A | ||||
| JP200167868A |
Foreign References:
| US20080068901 | ||||
| US20080068902 |
Attorney, Agent or Firm:
Makoto Hagiwara