Title:
半導体装置、及び電子機器
Document Type and Number:
Japanese Patent JP6599622
Kind Code:
B2
Abstract:
A novel semiconductor device that can write and read multilevel data is provided. A memory cell includes a bit line, a power supply line, first and second nodes, first to fourth transistors, and first and second capacitors. One of two divided multilevel data is written to the first node through the first transistor. The other of the divided multilevel data is written to the second node through the second transistor. A gate of the third transistor is connected to the first node, and a gate of the fourth transistor is connected to the second node. The third and fourth transistors control electrical continuity between the bit line and the power supply line. Each of the first and second transistors preferably includes an oxide semiconductor in a semiconductor layer.
Inventors:
Tomoaki Atami
Shuhei Nagatsuka
Shuhei Nagatsuka
Application Number:
JP2015050214A
Publication Date:
October 30, 2019
Filing Date:
March 13, 2015
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G11C11/405; G11C11/56; H01L21/8242; H01L27/108; H01L29/786
Domestic Patent References:
| JP201284851A | ||||
| JP2012198977A | ||||
| JP2012238374A | ||||
| JP2012256398A | ||||
| JP2015170749A |