Title:
スイッチングレギュレータ及び集積回路パッケージ
Document Type and Number:
Japanese Patent JP6603810
Kind Code:
B2
Abstract:
Provided is an integrated circuit package which complementarily switches on/off a MOS transistor Q1 (first switch) and MOS transistor Q2 (second switch) in accordance with an output voltage Vout, and which externally outputs a pulse signal having a fixed on-duty D during a step-up/step-down mode. The integrated circuit package has a determination unit 61 for determining the impedance of an external component connected to an external pin P5 that outputs the pulse signal to the exterior during the step-up/step-down mode, and determining whether the external component is a third switch on the basis of the impedance determination result.
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Inventors:
Shingo Hashiguchi
Tetsuo Tateishi
Tetsuo Tateishi
Application Number:
JP2018532966A
Publication Date:
November 06, 2019
Filing Date:
August 02, 2017
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
H02M3/155
Domestic Patent References:
| JP2015047040A | ||||
| JP2010267221A | ||||
| JP2007134119A |
Foreign References:
| WO2017002834A1 | ||||
| US20150054478 | ||||
| US20140153197 | ||||
| US20090262556 |
Attorney, Agent or Firm:
Sano patent office