Title:
高電圧ＭＯＳＦＥＴデバイスおよび該デバイスを製造する方法
Document Type and Number:
Japanese Patent JP6621749
Kind Code:
B2
Abstract:
A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.
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Inventors:
Banergie, Sugit
Matcha, Kevin
Chatty, Kairan
Matcha, Kevin
Chatty, Kairan
Application Number:
JP2016543982A
Publication Date:
December 18, 2019
Filing Date:
September 18, 2014
Export Citation:
Assignee:
Monolith Semiconductor Incorporated
International Classes:
H01L29/78; H01L21/336; H01L29/12
Domestic Patent References:
| JP61082477A | ||||
| JP8227993A | ||||
| JP2013110331A | ||||
| JP2013021242A | ||||
| JP1238174A | ||||
| JP2007234925A |
Foreign References:
| WO2010021146A1 | ||||
| WO2011033550A1 |
Attorney, Agent or Firm:
Takashima Ichi
Mitsunori Kamata
Kyoko Doi
Yaeko Tamura
Hirofumi Toma
Atsuko Akai
Tomiya Tozaki
Kitawaki Dai
Mitsunori Kamata
Kyoko Doi
Yaeko Tamura
Hirofumi Toma
Atsuko Akai
Tomiya Tozaki
Kitawaki Dai