Title:
サブブロック消去
Document Type and Number:
Japanese Patent JP6633295
Kind Code:
B2
Abstract:
A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.
Inventors:
Lu Hakoba
Zhang Guoqiang
Zhang Guoqiang
Application Number:
JP2015099178A
Publication Date:
January 22, 2020
Filing Date:
May 14, 2015
Export Citation:
Assignee:
Muang Hong Electronic Co., Ltd.
International Classes:
G11C16/16; G11C16/04; G11C16/08; G11C16/14
Domestic Patent References:
| JP2005025824A | ||||
| JP2013093577A | ||||
| JP2014135112A | ||||
| JP20134127A |
Foreign References:
| US20130107628 | ||||
| US20120051136 | ||||
| US20120120725 |
Attorney, Agent or Firm:
Tachibana Kenji
Yamada Iichiro
Hiroki Matsui
Junya Tanaka
Yamashita Unknown
Tsuyoshi Masuda
Yamada Iichiro
Hiroki Matsui
Junya Tanaka
Yamashita Unknown
Tsuyoshi Masuda