小型スプリットゲート不揮発性フラッシュメモリセル及びその作製方法

Title:

小型スプリットゲート不揮発性フラッシュメモリセル及びその作製方法

Document Type and Number:

Japanese Patent JP6701374

Kind Code:

B2

Abstract:

A reduced size non-volatile memory cell array is achieved by forming first trenches in an insulation layer in the row direction, filling the first trenches with insulation material, forming second trenches in the insulation layer in the column direction, forming the STI isolation material in the second trenches, and forming the source regions through the first trenches. Alternately, the STI isolation regions can be made continuous, and the source diffusion implant has sufficient energy to form continuous source line diffusions that each extend across the active regions and under the STI isolation regions. This allows control gates of adjacent memory cell pairs to be formed closer together.

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Inventors:

One Chun Min

Application Number:

JP2018550420A

Publication Date:

May 27, 2020

Filing Date:

March 27, 2017

Export Citation:

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Assignee:

SILICON STORAGE TECHNOLOGY, INC.

International Classes:

H01L21/336; H01L27/11521; H01L29/788; H01L29/792

Domestic Patent References:

JP2007300098A

Foreign References:

US20150021679
US20160086962

Attorney, Agent or Firm:

Shinichiro Tanaka
Disciple Maru Ken
▲吉▼田和彦
Fumiaki Otsuka
Takaki Nishijima
Hiroyuki Suda
Hiroshi Uesugi
Naoki Kondo
Takeo Nasu
Yoshinobu Iwasaki

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