Title:
集積回路を形成する方法およびそれに関連する集積回路
Document Type and Number:
Japanese Patent JP6725420
Kind Code:
B2
Abstract:
A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.
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Inventors:
Chan, Wenjia
Wyan, Beyond
Chang, Lee
Chu, Chao Ming
Michelle, Jurgen
Chua, Soo Jin
Pee, Li-Xuan
Cheer, Siauben
Lee, On Kian Kenneth
Wyan, Beyond
Chang, Lee
Chu, Chao Ming
Michelle, Jurgen
Chua, Soo Jin
Pee, Li-Xuan
Cheer, Siauben
Lee, On Kian Kenneth
Application Number:
JP2016546457A
Publication Date:
July 15, 2020
Filing Date:
January 14, 2015
Export Citation:
Assignee:
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
NATIONAL UNIVERSITY OF SINGAPORE
Nanyang Technological University
NATIONAL UNIVERSITY OF SINGAPORE
Nanyang Technological University
International Classes:
H01L27/15; G02B6/12; G02B6/13; H01L31/10
Domestic Patent References:
| JP9036413A | ||||
| JP2000082807A | ||||
| JP59129481A |
Foreign References:
| WO2013090140A1 |
Other References:
JINWOOK W. CHUNG,"Seamless On-Wafer Integration of Si(100)MOSFETs and GaN HEMTs",IEEE ELECTRON DEVICE LETTERS,2009年,vol. 30, no. 10,pages.1015 - 1017
Attorney, Agent or Firm:
Patent business corporation Yuko patent office