Title:
装置および方法
Document Type and Number:
Japanese Patent JP6731996
Kind Code:
B2
Abstract:
Methods and circuitry for low-speed bus time stamping and triggering are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that comprises a data line and a clock line. The master device generates and controls a clock signal on the clock line, and sends a synchronization command over the data line to the slave devices. In response to the synchronization command, the master device receives timestamp information of an event detected at each slave device. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can further send to each slave device delay setting information for generating a trigger signal at that slave device based on transitions of the clock signal, the synchronization command and the delay setting information.
Inventors:
Sharp-Geithler Bradley
Application Number:
JP2018227937A
Publication Date:
July 29, 2020
Filing Date:
December 05, 2018
Export Citation:
Assignee:
Lattice Semiconductor Corporation
International Classes:
G06F13/42; G06F13/24; G06F13/38
Domestic Patent References:
| JP2011211673A | ||||
| JP2015126314A | ||||
| JP2001267890A |
Foreign References:
| US20120243559 |
Attorney, Agent or Firm:
Shinji Hayami
Satoshi Amagi
Satoshi Amagi