Title:
半導体装置
Document Type and Number:
Japanese Patent JP6737379
Kind Code:
B2
Abstract:
To provide a semiconductor device which enables the suppression of a leak current and enables the achievement of high endurance against voltage.SOLUTION: A MOS gate structure is provided on a surface side of a silicon carbide semiconductor substrate arranged by depositing an n-type silicon carbide epitaxial layer 2 on an n-type silicon carbide substrate 1. The MOS gate structure comprises a p-type base region 3 which includes a first p-type base region 33a, a second p-type base region 33b and a third p-type base region 33c which are in contact with each other and different from each other in impurity density. The first p-type base region 33a is disposed and exposed on the surface of the substrate. The second p-type base region 33b is disposed so as to be opposed to the first p-type base region 33a in a depth direction. The third p-type base region 33c is selectively provided inside the second p-type base region 33b so as to be sandwiched between the first and second p-type base regions 33a and 33b. The periphery of the third p-type base region 33c on the substrate backside is surrounded by the second p-type base region 33b.SELECTED DRAWING: Figure 9
More Like This:
Inventors:
Akinori Kinoshita
Yasuyuki Hoshi
Yuichi Harada
Yasuhiko Onishi
Yasuyuki Hoshi
Yuichi Harada
Yasuhiko Onishi
Application Number:
JP2019103152A
Publication Date:
August 05, 2020
Filing Date:
May 31, 2019
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H01L29/78; H01L21/336; H01L29/06; H01L29/12; H01L29/739
Domestic Patent References:
| JP2007013087A | ||||
| JP2013232564A | ||||
| JP2013042075A |
Foreign References:
| WO2013172059A1 | ||||
| WO2011027540A1 |
Attorney, Agent or Firm:
Akinori Sakai