Title:
電界効果型トランジスタ
Document Type and Number:
Japanese Patent JP6764375
Kind Code:
B2
Abstract:
To provide an electrical field effect transistor capable of suppressing a short-channel effect effectively, without increasing parasitic capacity.SOLUTION: In an electrical field effect transistor where a buffer layer, a conduction channel layer, a spacer layer, a carrier layer and a barrier layer are laminated sequentially at a circuit formation side of a semiconductor substrate, and including two ohmic cap layers formed separately on the barrier layer, a source electrode and a drain electrode formed, respectively, on the two ohmic cap layers, and a gate electrode formed between the source electrode and the drain electrode on the barrier layer, a pole for electric field relaxation is formed while embedded in the semiconductor substrate so as not to come into contact with the conduction channel layer, at a position between the gate electrode and the drain electrode, at a back side of the semiconductor substrate, and the pole for electric field relaxation is configured so that a potential can be applied thereto.SELECTED DRAWING: Figure 3
Inventors:
Takuya Tsutsumi
Hideaki Matsuzaki
Hideaki Matsuzaki
Application Number:
JP2017124597A
Publication Date:
September 30, 2020
Filing Date:
June 26, 2017
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
H01L21/337; H01L21/338; H01L29/778; H01L29/808; H01L29/812
Domestic Patent References:
| JP2011060912A | ||||
| JP2011119366A | ||||
| JP2013182993A |
Foreign References:
| US20120068772 | ||||
| US20100065923 |
Attorney, Agent or Firm:
Patent Business Corporation Tani/Abe Patent Office