Title:
プロセッサ、情報処理装置及びプロセッサの動作方法
Document Type and Number:
Japanese Patent JP6767660
Kind Code:
B2
Abstract:
A processor includes: a first memory configured to store image data including pixel data of a plurality of pixels that are two-dimensionally arranged; a second memory configured to store neighborhood matrix image data including pixel data of a neighborhood matrix; and a format converter that includes (a) a readout circuit configured to read out the image data from the first memory, (b) a padding arithmetic unit configured to receive the read-out image data, select pixel data of the received read-out image data and padding data inserted at periphery of the plurality of pixels in accordance with mask values of a padding mask, and generate the neighborhood matrix image data including the pixel data and the padding data, and (c) a writing circuit configured to write the neighborhood matrix image data to the second memory.
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Inventors:
Katsuhiro Yoda
Mitsuru Banno
Takahiro Nozu
Mitsuru Banno
Takahiro Nozu
Application Number:
JP2017013398A
Publication Date:
October 14, 2020
Filing Date:
January 27, 2017
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F15/80; G06T1/20; G06F17/10; G06T5/20
Domestic Patent References:
| JP2012118699A | ||||
| JP2009199491A | ||||
| JP2006094160A | ||||
| JP2000020705A |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku