Title:
エピタキシャルウェーハの製造方法
Document Type and Number:
Japanese Patent JP6770720
Kind Code:
B2
Abstract:
According to the present invention, silicon semiconductor substrates are prepared so as to have polished rear surfaces, and the substrates thus prepared are cleansed and then placed in a substrate storage part 2 in a batch consisting of more than one substrate. The atmosphere in the substrate storage part 2 is controlled so as to contain NO2 and NO3 in a total concentration of at most 140 ng/m3. The substrates stored in the substrate storage part 2 are conveyed, one by one, to a reactor 5, in which a silicon epitaxial layer is formed by vapor phase epitaxy. Accordingly, provided is a method that suppresses the generation of a rear surface halo dependent on time passage following the cleaning of substrates, and that enables manufacturing of high-grade epitaxial wafers.
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Inventors:
Ryosuke Iwamoto
Osamu Onishi
Osamu Onishi
Application Number:
JP2017208267A
Publication Date:
October 21, 2020
Filing Date:
October 27, 2017
Export Citation:
Assignee:
Shin-Etsu Semiconductor Co., Ltd.
International Classes:
H01L21/205; C23C16/02; C23C16/24; H01L21/20
Domestic Patent References:
| JP2001167995A |
Foreign References:
| WO2016190360A1 | ||||
| WO2002053267A1 |
Attorney, Agent or Firm:
Ryuji Harikawa
Kengo Yamauchi
Kengo Yamauchi