Title:
半導体集積回路、半導体集積回路における制御方法、画像処理装置
Document Type and Number:
Japanese Patent JP6771233
Kind Code:
B2
Abstract:
To provide a semiconductor integrated circuit capable of suppressing the complication of a circuit and an increase in a manufacturing cost, and suppressing a deterioration in processing capability in transiting from a standby state to an operating state, and a game machine.SOLUTION: A semiconductor integrated circuit includes a first circuit part A10 having a plurality of flip flop circuits 13, 13,...13, and a second circuit part B10 having flip flop circuits 22, 22,...22. A whole clock gating part 11 included in the first circuit part A10 interrupts a clock signal to the first circuit part A10 in a standby state, and causes the clock signal to pass in an operating state, and individual clock gating parts 21, 21,...21included in the second circuit part B10 cause a clock signal to pass to the flip flop circuits 22, 22,...22in a standby state, and interrupt a clock signal that is not rewritten to data in an operating state.SELECTED DRAWING: Figure 1
Inventors:
Atsushi Kikuchi
Application Number:
JP2018134300A
Publication Date:
October 21, 2020
Filing Date:
July 17, 2018
Export Citation:
Assignee:
Accel Corporation
International Classes:
G06F1/04; H01L21/822; H01L27/04
Domestic Patent References:
| JP2016119003A | ||||
| JP2001134341A | ||||
| JP2016212554A | ||||
| JP2003141198A |
Foreign References:
| US20160179176 |
Attorney, Agent or Firm:
Hiroshi Sano
Akio Ishii
Akio Ishii