Title:
再構成可能論理回路
Document Type and Number:
Japanese Patent JP6786955
Kind Code:
B2
Abstract:
A reconfigurable logical circuit includes a data processing unit; a memory in which plural combinations of configuration control bits are stored; and a selector unit that selectively switches the plural combinations of configuration control bits stored in the memory and supplies a selected one of the plural combinations of configuration control bits to the data processing unit to reconfigure processing contents of the data processing unit.
Inventors:
Hisagi nori
Masatomo Igarashi
Masahiro Ishiwatari
Uchiyama Junichi
Sasaki Hifumi
Mitsuyuki Tamaya
Kazuo Yamada
Masatomo Igarashi
Masahiro Ishiwatari
Uchiyama Junichi
Sasaki Hifumi
Mitsuyuki Tamaya
Kazuo Yamada
Application Number:
JP2016164829A
Publication Date:
November 18, 2020
Filing Date:
August 25, 2016
Export Citation:
Assignee:
Fuji Xerox Co., Ltd
International Classes:
H03K19/173
Domestic Patent References:
| JP200631127A | ||||
| JP2008225662A | ||||
| JP2010539582A |
Attorney, Agent or Firm:
Patent Corporation yki International Patent Office