Title:
二次元実行レーンアレイおよび二次元シフトレジスタを有する画像プロセッサのためのブロック処理
Document Type and Number:
Japanese Patent JP6821715
Kind Code:
B2
Abstract:
A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.
Inventors:
Makesner, Albert
Finchel Stein, Daniel Frederick
David Patterson
Mark, William Earl
Redgrave, Jason Rupert
Shacham, Ofer
Finchel Stein, Daniel Frederick
David Patterson
Mark, William Earl
Redgrave, Jason Rupert
Shacham, Ofer
Application Number:
JP2018567828A
Publication Date:
January 27, 2021
Filing Date:
June 08, 2017
Export Citation:
Assignee:
Google LLC
International Classes:
G06T1/20; G06F17/10; G06F17/14; G06F17/16
Domestic Patent References:
| JP2098790A | ||||
| JP2007004542A |
Other References:
尼崎 太樹、他(著)、天野 英晴(編),6章 ハードウェアアルゴリズム、6・3 シストリックアルゴリズム,FPGAの原理と構成,日本,株式会社オーム社,2016年 4月25日,pp. 172-179
Attorney, Agent or Firm:
Fukami patent office