Title:
半導体装置を製造する方法
Document Type and Number:
Japanese Patent JP6859708
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent generation of a void successfully to achieve a semiconductor device having good connection and excellent reflow resistance properties in semiconductor device manufacturing including connection of connection parts with each other by metal joining.SOLUTION: A semiconductor device manufacturing method comprises in the following order the steps of: sandwiching a laminate which has a semiconductor chip, a semiconductor wafer including a substrate or another semiconductor chip or a part corresponding to the other semiconductor chip and a setting adhesive layer arranged between the semiconductor chip and the semiconductor wafer by a pair of pressing members to pressure bond the substrate or the other semiconductor chip or the semiconductor wafer to the semiconductor chip; promoting curing reaction of the setting adhesive layer; and electrically connecting a connection part of the semiconductor chip with a connection part of the substrate or the other semiconductor chip by metal joining.SELECTED DRAWING: Figure 1
Inventors:
Kazutaka Honda
Shin Sato
Chaka Koichi
Shin Sato
Chaka Koichi
Application Number:
JP2017001729A
Publication Date:
April 14, 2021
Filing Date:
January 10, 2017
Export Citation:
Assignee:
Showa Denko Materials Co., Ltd.
International Classes:
H01L21/60
Domestic Patent References:
| JP2012044155A | ||||
| JP2013173834A | ||||
| JP2013187491A | ||||
| JP2009277823A |
Attorney, Agent or Firm:
Yoshiki Hasegawa
Yoshinori Shimizu
Hiroyuki Hirano
Hideki Okita
Yoshinori Shimizu
Hiroyuki Hirano
Hideki Okita