Title:
レートデマッチング及びデインターリーブ回路
Document Type and Number:
Japanese Patent JP6863661
Kind Code:
B2
Abstract:
To provide a rate de-matching and de-interleave circuit capable of realizing a high throughput without using any means by which a circuit operation frequency is raised.SOLUTION: An even-numbered row data storage circuit 11 which stores data of even-numbered rows in terms of code block and an odd-numbered row data storage circuit 12 which stores data of odd-numbered rows of received data in terms of code block are provided. A head position storage circuit 4 stores which of the even-numbered row data storage circuit 11 and the odd-numbered row data storage circuit 12 was firstly used when starting data writing in terms of row. A read-out address generation part 3 generates a read-out address from the even-numbered row data storage circuit 11 and the odd-numbered row data storage circuit 12 by using the data stored by the head position storage circuit 4.SELECTED DRAWING: Figure 6
Inventors:
Hidenori Sato
Hiroki Iwahara
Hiroki Iwahara
Application Number:
JP2017113324A
Publication Date:
April 21, 2021
Filing Date:
June 08, 2017
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H03M13/27; H04L1/00
Domestic Patent References:
| JP2015130128A | ||||
| JP2012099989A |
Foreign References:
| WO2006082923A1 | ||||
| US20130182805 | ||||
| WO2002062001A1 |
Attorney, Agent or Firm:
Hamada Hatsune
Nakashima Shigeru
Tatsuya Sakamoto
Tsujioka Masaaki
Kazuma Inoue
Nakashima Shigeru
Tatsuya Sakamoto
Tsujioka Masaaki
Kazuma Inoue