Title:
グランドプレーンから分離されたインジケータ回路
Document Type and Number:
Japanese Patent JP6888053
Kind Code:
B2
Abstract:
The invention is directed towards an indicator circuit. The indicator circuit includes a ground plane; an antenna; a decoupler component; and an integrated circuit. The antenna includes at least one antenna trace; a first antenna terminal; and a second antenna terminal. The decoupler component includes a first decoupler component terminal and a second decoupler component terminal. The integrated circuit is electrically coupled to the first antenna terminal and the second antenna terminal. The integrated circuit is electrically coupled to the first decoupler component terminal. The second decoupler component terminal is electrically connected to the ground plane.
Inventors:
Alistair, Neil, Chapel
Jerome, Alexander, Martin, Delay
Calvin, Christopher, Giles
Konstantin, Dimitrov, Stefanov
Matthew, Emmanuel, Milton, Stokey
Jordan, Todorov, Bourylkov
Sergio, Coronado, Holtar
William, Fitler, Morris
Steven, Jeffrey, Spect
Jerome, Alexander, Martin, Delay
Calvin, Christopher, Giles
Konstantin, Dimitrov, Stefanov
Matthew, Emmanuel, Milton, Stokey
Jordan, Todorov, Bourylkov
Sergio, Coronado, Holtar
William, Fitler, Morris
Steven, Jeffrey, Spect
Application Number:
JP2019132998A
Publication Date:
June 16, 2021
Filing Date:
July 18, 2019
Export Citation:
Assignee:
Duracell, US, Operations, Incorporated
International Classes:
H01Q7/00; H01M10/42; H01M10/48; H01Q1/24; H02J7/00
Domestic Patent References:
JP2012124141A | ||||
JP2010092760A | ||||
JP2016530742A | ||||
JP2016518006A | ||||
JP2010081716A | ||||
JP2006139544A | ||||
JP2012170262A |
Foreign References:
US5587573 | ||||
WO2013101652A1 |
Attorney, Agent or Firm:
Hiroyuki Nagai
Yukitaka Nakamura
Satoru Asakura
Hiroshi Yoshimoto
Yukitaka Nakamura
Satoru Asakura
Hiroshi Yoshimoto