Title:
配線基板および電子モジュール
Document Type and Number:
Japanese Patent JP6888668
Kind Code:
B2
Abstract:
A wiring substrate that is provided enables stray capacitance between a first electrode and a second electrode to be prevented from varying when an undulation occurs in the wiring substrate. Insulating layers are stacked. A first electrode and a second electrode are formed between the same layers at an interval. The thickness of the first electrode is more than the thickness of the second electrode. The lower main surface of the first electrode is located at a position lower than the lower main surface of the second electrode, and the upper main surface of the first electrode is located at a position higher than the upper main surface of the second electrode when seen through in a direction perpendicular to a stacking direction of the insulating layers.
Inventors:
Ryota Asai
Yamamoto Issei
Yamamoto Issei
Application Number:
JP2019509747A
Publication Date:
June 16, 2021
Filing Date:
March 24, 2018
Export Citation:
Assignee:
MURATA MANUFACTURING CO.,LTD.
International Classes:
H05K3/46; H01L23/13; H01L25/00; H05K1/16
Domestic Patent References:
| JP2001085801A | ||||
| JP2005347354A | ||||
| JP2013062293A | ||||
| JP9237955A |
Attorney, Agent or Firm:
Nao Kawamoto