Title:
半導体ウエハ及びその製造方法
Document Type and Number:
Japanese Patent JP6893889
Kind Code:
B2
Abstract:
To provide a semiconductor wafer having a low resistivity.SOLUTION: A semiconductor wafer includes a diffusion layer 11a doped with a second impurity d2, at least in a part of a wafer comprising a semiconductor material s and a first impurity d1 which are melted therein. The sum of concentrations of the first impurity and the second impurity in the diffusion layer is a higher concentration than solubility of the first impurity at the melting point of the semiconductor material. A method of producing a semiconductor wafer includes: a single crystal preparation step (a) of preparing a single crystal ingot 1 comprising a semiconductor material and a first impurity which are melted therein; a slice step (b) of slicing the ingot to prepare a wafer 11; and a diffusion step (c) of forming a diffusion layer including a second impurity doped therein, at least in a part of the wafer. In the diffusion step, the second impurity is doped at least into a part of the wafer such that the concentration of the second impurity is a higher concentration than the solubility of the first impurity at the melting of the semiconductor material in the single crystal preparation step.SELECTED DRAWING: Figure 1
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Inventors:
Tadashi Ibaraki
Onishi Riki
Onishi Riki
Application Number:
JP2018001768A
Publication Date:
June 23, 2021
Filing Date:
January 10, 2018
Export Citation:
Assignee:
Naoetsu Electronics Industry Co., Ltd.
International Classes:
H01L21/22; C30B33/00
Domestic Patent References:
| JP11008201A | ||||
| JP2017037984A | ||||
| JP2006032463A | ||||
| JP2012074664A |
Attorney, Agent or Firm:
Eichi International Patent Office