Title:
ハイエンドマイクロコントローラ用のマルチダイにおけるスケーラブルなマルチコア型のシステムオンチップアーキテクチャ
Document Type and Number:
Japanese Patent JP6895939
Kind Code:
B2
Abstract:
A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.
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Inventors:
Frank Helwig
Albrecht Meier
Yeak Shapers
Albrecht Meier
Yeak Shapers
Application Number:
JP2018210728A
Publication Date:
June 30, 2021
Filing Date:
November 08, 2018
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
G06F13/36; G06F13/38; G06F15/78
Foreign References:
| WO2015099719A1 | ||||
| US20150169495 | ||||
| US20150249602 | ||||
| US20150357306 | ||||
| US20030131228 | ||||
| US8949474 |
Attorney, Agent or Firm:
Einzel Felix-Reinhard
Morita Taku
Junichi Maekawa
Hiroyasu Ninomiya
Ueshima
Morita Taku
Junichi Maekawa
Hiroyasu Ninomiya
Ueshima
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