Title:
データ転送装置、演算処理装置及びデータ転送方法
Document Type and Number:
Japanese Patent JP6905195
Kind Code:
B2
Abstract:
An apparatus includes a processor, first and second request-controllers, and a buffer. The processor divides a data-transfer request into transfer-requests including first and second transfer-requests. When, within a memory, an end-address of readout data based on the first transfer-request is adjacent to a head-address of readout data based on the second transfer-request, the processor sets end-adjacency information in the first transfer-request and sets head-adjacency information in the second transfer-request. Then, the first request-controller sets first adjacency information in a first readout-request for a readout end-address of the first transfer-request. The second request-controller sets second adjacency information in a second readout-request for a readout head-address of the second transfer-request. In response to the first readout-request, the buffer retains data read out from the memory, and outputs the data to the first request-controller. In response to the second readout-request, the buffer outputs the retained data to the second request-controller.
Inventors:
Masahiro Mishima
Application Number:
JP2017220674A
Publication Date:
July 21, 2021
Filing Date:
November 16, 2017
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F13/28
Domestic Patent References:
| JP10171750A | ||||
| JP2005332125A |
Foreign References:
| WO2004057481A1 | ||||
| US20140059052 |
Attorney, Agent or Firm:
Takayoshi Kokubun