Title:
半導体装置
Document Type and Number:
Japanese Patent JP6909629
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device which can ensure heat dissipation properties while reducing concentration of thermal stress acting on a sealing resin.SOLUTION: A semiconductor device comprises: a die pad 1 having a mounting surface 11 and a pad rear face 12; a semiconductor element 2 mounted on the mounting surface 11; a plurality of terminals 3 which are arranged to surround the die pad 1 and electrically connected with the semiconductor element 2; and a sealing resin 5 which has a resin rear face 52 facing the same direction with a pad rear face 12 and partially covers the semiconductor element 2, the die pad 1 and the plurality of terminals 3. Both of the pad rear face 12 and the terminal rear face 32 are exposed from the resin rear face 52; and pad recesses 14 denting from the pad rear face 12 are formed on the die pad 1.SELECTED DRAWING: Figure 2
More Like This:
JPH04134835 | HYBRID INTEGRATED CIRCUIT DEVICE |
WO/2020/115830 | SEMICONDUCTOR DEVICE AND ANTENNA DEVICE |
JPH0376148 | HYBRID INTEGRATED CIRCUIT DEVICE |
Inventors:
Masato Ikeda
Application Number:
JP2017093698A
Publication Date:
July 28, 2021
Filing Date:
May 10, 2017
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
H01L23/50
Domestic Patent References:
JP2011091145A | ||||
JP2017028200A | ||||
JP2013239740A | ||||
JP2009507394A | ||||
JP2009071154A | ||||
JP1204460A | ||||
JP2001077278A |
Foreign References:
WO2002061835A1 | ||||
US20070052070 |
Attorney, Agent or Firm:
Minoru Yoshida
Nao Usui
Nao Usui