Title:
マルチスレッドプロセッサの命令キャッシュ
Document Type and Number:
Japanese Patent JP6918051
Kind Code:
B2
Abstract:
A processor is disclosed including: a barrel-threaded execution unit for executing concurrent threads, and a repeat cache shared between the concurrent threads. The processor's instruction set includes a repeat instruction which takes a repeat count operand. When the repeat cache is not claimed and the repeat instruction is executed in a first thread, a portion of code is cached from the first thread into the repeat cache, the state of the repeat cache is changed to record it as claimed, and the cached code is executed a number of times. When the repeat instruction is then executed in a further thread, then the already-cached portion of code is again executed a respective number of times, each time from the repeat cache. For each of the first and further instructions, the repeat count operand in the respective instruction specifies the number of times to execute the cached code.
Inventors:
Alan graham alexander
Simon Christian Knowles
Mardura Goa
Jonathan Louis Ferguson
Simon Christian Knowles
Mardura Goa
Jonathan Louis Ferguson
Application Number:
JP2019113318A
Publication Date:
August 11, 2021
Filing Date:
June 19, 2019
Export Citation:
Assignee:
Graphcore Limited
International Classes:
G06F9/32; G06F9/30; G06F9/38; G06F9/46; G06F12/0842; G06F12/0875
Domestic Patent References:
| JP2019079530A | ||||
| JP2017228213A | ||||
| JP2013541758A | ||||
| JP2011070695A | ||||
| JP2004516571A | ||||
| JP2002268878A | ||||
| JP11073318A | ||||
| JP60241136A | ||||
| JP2010538398A |
Foreign References:
| WO2018169911A1 | ||||
| WO2008155834A1 | ||||
| US20150220347 | ||||
| US20080155236 | ||||
| US7178013 |
Attorney, Agent or Firm:
Murai Koji
Nao Watanabe
Nao Watanabe