Title:
演算処理装置および演算処理装置の制御方法
Document Type and Number:
Japanese Patent JP6926727
Kind Code:
B2
Abstract:
An operation processing device includes a first register unit including first registers configured to hold data to be used for an operation in an operation unit; a first selection unit that selects data held by a first register indicated by a read address signal; a second selection unit that selects, based on a bypass selection signal, data from a data group including the data selected by the first selection unit and data indicative of a result of the operation; a second register unit that outputs the data selected by the second selection unit to the operation unit; a timing adjustment unit that outputs the read address signal to the first selection unit; and a bypass control unit that stops an operation of the timing adjustment unit when generating the bypass selection signal indicative of a selection of data other than the data selected by the first selection unit.
Inventors:
Seiji Hirao
Sota Sakashita
Sota Sakashita
Application Number:
JP2017126750A
Publication Date:
August 25, 2021
Filing Date:
June 28, 2017
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F9/38; G06F9/34
Domestic Patent References:
| JP2008542949A | ||||
| JP8272611A | ||||
| JP5143328A |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Tadahiko Ito