Title:
周辺充填および局在化容量
Document Type and Number:
Japanese Patent JP6946534
Kind Code:
B2
Abstract:
Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a memory cell having one or two transistors, or other switching components, and one capacitor, such as a ferroelectric or dielectric capacitor, may be electrically isolated from one or more containers sharing a common access line, and the isolated containers may be used as capacitors. The capacitors may be used for filtering in some examples. Or the capacitance may be used to boost or regulate voltage in, for example, support circuitry.
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Inventors:
Kawamura, Christopher John
Scott James, Durner
Scott James, Durner
Application Number:
JP2020169614A
Publication Date:
October 06, 2021
Filing Date:
October 07, 2020
Export Citation:
Assignee:
Micron Technology, Ink.
International Classes:
G11C11/22; G11C5/02; G11C11/407
Domestic Patent References:
| JP2000188382A | ||||
| JP2002124081A | ||||
| JP684359A |
Foreign References:
| US20150311217 | ||||
| US20140233336 |
Attorney, Agent or Firm:
Hiroyoshi Aoki
Amada Masayuki
Yoshiyuki Osuga
Amada Masayuki
Yoshiyuki Osuga