Title:
通信装置、通信方法、プログラム、および、通信システム
Document Type and Number:
Japanese Patent JP6953226
Kind Code:
B2
Abstract:
Communication is performed more reliably. A CCI (I3C DDR) processing section determines status of an index when requested to be accessed by an I3C master for a read operation. An error handling section then controls an I3C slave 13 to detect occurrence of an error based on the status of the index and to neglect all communication until DDR mode is stopped or restarted by the I3C master, the I3C slave 13 being further controlled to send a NACK response when performing acknowledge processing on a signal sent from the I3C master. This technology can be applied to the I3C bus, for example.
Inventors:
Hiroo Takahashi
Naohiro Koshisaka
Naohiro Koshisaka
Application Number:
JP2017152062A
Publication Date:
October 27, 2021
Filing Date:
August 04, 2017
Export Citation:
Assignee:
Sony Semiconductor Solutions Corporation
International Classes:
G06F13/42; G06F11/07; H04L1/00; H04L1/16
Domestic Patent References:
| JP2016539533A | ||||
| JP2008186130A |
Foreign References:
| US20150100862 | ||||
| US20080181206 |
Attorney, Agent or Firm:
Takashi Nishikawa
Yoshio Inamoto
Yoshio Inamoto