Title:
ハイブリッドメモリキューブシステム相互接続ディレクトリベースキャッシュコヒーレンス方法
Document Type and Number:
Japanese Patent JP6953488
Kind Code:
B2
Abstract:
A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.
Inventors:
Radel, John Dee.
Murphy, Richard Sea.
Murphy, Richard Sea.
Application Number:
JP2019168477A
Publication Date:
October 27, 2021
Filing Date:
September 17, 2019
Export Citation:
Assignee:
Micron Technology, Ink.
International Classes:
G06F12/0817; G06F12/1072; G11C5/04
Domestic Patent References:
| JP2005234854A | ||||
| JP2007199999A | ||||
| JP2012514286A | ||||
| JP2008046701A | ||||
| JP2009116398A |
Foreign References:
| US20050198441 | ||||
| US20070174557 | ||||
| US20100165692 | ||||
| WO2014178854A1 | ||||
| US20130347110 | ||||
| US20120106228 | ||||
| US20040088495 | ||||
| WO2012077169A1 |
Attorney, Agent or Firm:
Hiroyoshi Aoki
Amada Masayuki
Yoshiyuki Osuga
Nomura Yasuhisa
Amada Masayuki
Yoshiyuki Osuga
Nomura Yasuhisa