ＤＲＡＭのリフレッシュ管理 - ADVANCED MICRO DEVICES INCORPORATED

Title:

ＤＲＡＭのリフレッシュ管理

Document Type and Number:

Japanese Patent JP7357169

Kind Code:

B2

Abstract:

A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

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Inventors:

Kevin M. Brundle
Kedanash Barakrishnan
Jin Wan
Guanghao Shen

Application Number:

JP2022567615A

Publication Date:

October 05, 2023

Filing Date:

April 27, 2021

Export Citation:

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Assignee:

ADVANCED MICRO DEVICES INCORPORATED

International Classes:

G06F12/00; G11C11/408

Domestic Patent References:

JP2020166832A
JP2020521267A
JP2016504702A

Foreign References:

US20190228813
WO2018215715A1

Attorney, Agent or Firm:

Yuji Hayakawa
Ryota Sano
Keisuke Murasame

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