Title:
単一のトランジスタ乗算器およびその方法
Document Type and Number:
Japanese Patent JP7412010
Kind Code:
B2
Abstract:
A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET. An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents. In a next reset phase, the second capacitor holds a multiplied value of charge.
More Like This:
| JPS52146144 | ANALOG MULTIPLICATION DIVISION APPARATUS |
Inventors:
Sea, David
Gaitekevic, Sergei
Dravos, Peter
Sibri, Andreas
Sibri, Eric
Gaitekevic, Sergei
Dravos, Peter
Sibri, Andreas
Sibri, Eric
Application Number:
JP2020568949A
Publication Date:
January 12, 2024
Filing Date:
March 04, 2019
Export Citation:
Assignee:
AISTORM,INC.
International Classes:
G06G7/16; G06G7/60; G06N3/063
Domestic Patent References:
| JP49021818B1 | ||||
| JP2010061428A |
Foreign References:
| US20160315588 |
Attorney, Agent or Firm:
Patent Attorney Corporation Hiroe Associates Patent Office