Title:
半導体装置およびその制御方法
Document Type and Number:
Japanese Patent JP7461868
Kind Code:
B2
Abstract:
A semiconductor device includes a flash memory including a plurality of electrically erasable memory cells and configured to output a verification result signal indicating whether erasing is succeeded or not, and a control block configured to control the flash memory. The control block includes a batch erasing range control circuit indicating a collectively erased range in the flash memory. When the verification result signal VR indicates failure of erasing of sectors in a first range specified by the batch erasing range control circuit after the erasing is executed, a second range for which erasing is to be executed again is calculated on the basis of a failure sector address that specifies a sector for which the erasing is failed and an end sector address that specifies an end of the first range, the specified second range is set to the batch erasing range control circuit, and erasing sectors in the second range is executed.
Inventors:
Masafumi Hayakawa
Application Number:
JP2020216102A
Publication Date:
April 04, 2024
Filing Date:
December 25, 2020
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G11C16/16; G11C16/34
Domestic Patent References:
| JP2002170389A | ||||
| JP2001126489A | ||||
| JP6259977A | ||||
| JP5325576A | ||||
| JP5182479A |
Foreign References:
| US20150221388 | ||||
| US6421276 |
Attorney, Agent or Firm:
Patent Attorney Tsutsui International Patent Office