Document Type and Number:
Japanese Patent JPH0120553
Kind Code:
B2
Abstract:
PURPOSE:To increase the switching speed by a method wherein a floating gate and a control gate arranged adjacent to each other via an insulating film are unevenly arranged in the region which is to be the source or drain. CONSTITUTION:A field oxide film 102 and an island-shaped oxide film 103 are formed on a p-type silicon substrate. Then, a control gate 104 consisting of poly-crystalline silicon and a poly-crystalline silicon film 106 are formed on it. Then, anisotropy etching is performed to remove the film 106, with the poly-crystalline silicon film 106' left. Then, the film 106 is selectively etched away to form a floating gate 107. After an oxide film is formed around the gate 107, ions are implanted. Then, the arsenic into which ions are implanted is activated to form n<+> type impurity diffusion layers 109 and 110. Then, an SiO2 film is laminated to form Al electrodes 113 and 114.
Inventors:
MIZUTANI YOSHIHISA
Application Number:
JP3567885A
Publication Date:
April 17, 1989
Filing Date:
February 25, 1985
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/28; H01L21/8247; H01L29/788; H01L29/792
Next Patent: JPH0120554