Document Type and Number:
Japanese Patent JPH0122990
Kind Code:
B2
Abstract:
PURPOSE:To improve inferior withstand voltage, etc., of semiconductor memory unit by a method wherein a thin oxide film is formed on a memory cell region and a thick oxide film is formed on a circumferential circuit region separated with each other, and the first gate electrode of the memory and a gate electrode of the circumferential circuit are formed by the same polycrystalline Si layer. CONSTITUTION:A thick field oxide film 102 is provided on a p type Si substrate 101, plural island type regions are formed, the thin gate oxide film 110 is provided on the memory cell region, and the thick gate oxide film 111 is provided on the circumferential circuit region. Then the polycrystalline Si layer is provided on the whole surface, and after the first gate electrode 108 and the gate electrode 109 are formed by patterning, the surface is oxidized, and after the second electrode 114 is provided, the oxide film at the unnecessitated part is removed, and n type regions 116-118 are formed by diffusion. Accordingly short-circuit and inferior withstand voltage at the circumferential circuit are prevented, and moreover capacitance of the two layers gate memory cell can be enlarged to enhance reliability.
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Inventors:
MATSUMOTO YASUO
IWAI HIROSHI
IWAI HIROSHI
Application Number:
JP2278181A
Publication Date:
April 28, 1989
Filing Date:
February 18, 1981
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L27/10; H01L27/108; H01L29/78
Next Patent: JPH0122991