Japanese Patent JPH0133856

B2

PURPOSE:To perform page fault processing at a high speed without increasing overhead, by storing the address of an instruction, etc., interrupted according to a page fault signal, in a store buffer temporarily and by handling it when the instruction is restarted. CONSTITUTION:Once a page fault occurs, the contents of an address register 26 are transferred to a store buffer 38, wherein the same contents as those written in a cash register consisting of a directory part 29 and a data part 30 in writing operation, temporarily according to an interruption instruction. Simultaneously, an interruption signal is generated and when page fault processing ends, reading operation is restarted by an instruction which corresponds to an address, etc., held in the buffer 38 temporarily. In case of an error page fault during writing operation, the address of a next instruction is stored in the buffer 38 after the writing operation ends and restarting processing is performed similarly. Therefore, the need to make an address check or to retain instruction input data before reading and writing operation is eliminated, and the page fault processing is performed at a high speed without increasing an overhead.

BANDO TADAAKI
MATSUMOTO HIDEKAZU
FUKUNAGA YASUSHI
HIRAOKA YOSHINARI
IDE TOSHUKI
KAWAKAMI TETSUYA

JP17586380A

July 17, 1989

December 15, 1980

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HITACHI SEISAKUSHO KK
HITACHI ENJINIARINGU KK

G06F12/08; G06F12/10

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