Document Type and Number:
Japanese Patent JPH0211173
Kind Code:
B2
Abstract:
An interpolation or smoothing filter circuit for a switched-capacitor system which transforms the sampled-and-held output signals from a switched-capacitor filter into sampled-and-held signals with a doubled sample rate. The circuit comprises an operational amplifier whose noninverting input lead is connected to a switched capacitor network which receives the sampled-and-held input signals at the normal sample rate. The network includes two separate capacitors controlled by switches operable at two alternating clock phases and connected to provide the desired summation and holding of charges. Feedback leads connected between the amplifier output lead and its noninverting input lead and containing additional capacitors cooperate with the input network to produce an output signal that is sampled-and-held at twice the sample rate of the input signal.
Inventors:
GUREGORIAN RUUBITSUKU
SUZUKI TOSHIRO
SUZUKI TOSHIRO
Application Number:
JP50213081A
Publication Date:
March 13, 1990
Filing Date:
May 21, 1981
Export Citation:
Assignee:
AMERIKAN MAIKURO SHISUTEMUSU INC
HITACHI SEISAKUSHO KK
HITACHI SEISAKUSHO KK
International Classes:
H03H17/00; H03H19/00
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