Japanese Patent JPH0230887

B2

A vehicle speed control system is disclosed in which a signal (Vs) representing actual vehicle speed is, when the vehicle is running at a desired speed, mementarily fed into, and then stored in, a memory (36). The memory therefore produces a signal (Vm) representing desired speed. An error amplifier (42) compares the signal (Vm) with a signal (Vf) which represents actual vehicle speed and which is derived from Vs via a filter (381. Any speed error causes a drive circuit (46) to adjust the throttle (15) of the vehicle engine (10) so as to tend to correct the vehicle speed error. The vehicle-speed-dependent signal (Vf) is derived from the actual speed of the engine (10) of the vehicle, and this signal is also fed to a comparator (50) which compares it with a reference signal (Vr) representing an upper or lower limit for engine speed. When the comparison indicates that the engine speed has exceeded the level represented by the reference Vr (e.g. when the vehicle transmission is inadvertently disconnected), a control unit (56) switches off the vehicle speed control system. If Vf is derived not from the actual speed of the engine of the vehicle but from its road speed, then a separate circuit producing an actual engine speed signal, for comparison with the engine speed limit signal Vr, may be used.

NOTSUDEINGUSU JON
BOOTON ROORANDO KENESU

JP50067079A

July 10, 1990

April 27, 1979

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B60K31/00; B60K31/02; B60K31/10; F02D29/00; F02D31/00; F02D35/00; F02D45/00; G05D13/62

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