Japanese Patent JPH024016

B2

PURPOSE:To increase the processing speed by changing the bit of a TLB (translation look-aside buffer) entry of a page immediately preceding the page of a TLB entry to be replaced. CONSTITUTION:A virtual address is loaded to an MAR32 in order to give memory access to a main memory 10. Then the intra-page offset contained in the loaded virtual address of the MAR32 is led to a boundary checking circuit 36. The circuit 36 checks whether or not an access covers a page boundary as long as the memory access given to the memory 10 is equal to full-word access. In this example, a page equal to 2KB and therefore the Offset contains 11 bits. In such a case, it is just required for the circuit 36 to check whether the Offset is shown or not as ''7FE'' in the hexadecimal expression as long as the memory access is equal to full-word access of a half-word boundary. The result of this check is delivered to a control circuit 37 in the form of a signal PAGEBD.

EGUCHI KAZUTOSHI

JP13590684A

January 25, 1990

June 30, 1984

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TOKYO SHIBAURA ELECTRIC CO

G06F12/10

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