Document Type and Number:
Japanese Patent JPH024145
Kind Code:
B2
Abstract:
A circuit arrangement includes an integrated semiconductor circuit with a plurality of connection leads in which stray capacitances with equal temperature coefficients exist between one connection lead and the two adjacent, second and third, connection leads. A voltage is present between the first and second connection leads, and produces a current through the stray capacitance between these connection leads. In order to cancel the effect of this temperature-dependent current, a compensation voltage is applied between the first and second connection leads, which compensation voltage causes a current which is equal and opposite to the current through the stray capacitance between the first and second connection leads to flow through the stray capacitance between the first and third connection leads.
Inventors:
KOODO HAINRITSUHI KOOSHIIKU
Application Number:
JP8897382A
Publication Date:
January 26, 1990
Filing Date:
May 27, 1982
Export Citation:
Assignee:
FUIRITSUPUSU FURUUIRANPENFUABURIKEN NV
International Classes:
H05K1/02; H01L21/82; H01L21/822; H01L23/64; H01L27/04; H03B5/12; H03F1/14; H03L1/00
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