Title:
【発明の名称】集積回路用トレンチセル
Document Type and Number:
Japanese Patent JPH02501251
Kind Code:
A
Abstract:
A multiple element integrated circuit trench cell having at least one vertical field effect transistor (FET) in a wall of a trench in a semiconductor substrate. The cell further comprises a central load device within the trench which is electrically connected to the vertical FET. The central load device may be an active load device, such as another field effect transistor, or a passive load device, such as a resistor. Additionally, a further FET may be present in another wall of the trench or in a lateral orientation adjacent the trench in the semiconductor surface. Two of these multiple element trench cells may be interconnected in various configurations to form conventional static random access memory (SRAM) cells.
Inventors:
Marten
Wan, Karl El
Nguyen, Vitien
Woo, way
Wan, Karl El
Nguyen, Vitien
Woo, way
Application Number:
JP50770788A
Publication Date:
April 26, 1990
Filing Date:
August 12, 1988
Export Citation:
Assignee:
Motorola Incorporated
International Classes:
G11C11/412; H01L21/8244; H01L27/06; H01L27/088; H01L27/11; H01L29/78; (IPC1-7): H01L27/11; G11C11/412
Attorney, Agent or Firm:
Kugoro Tamamushi