Document Type and Number:
Japanese Patent JPH026453
Kind Code:
B2
Abstract:
A dynamic amplifier comprises two complementary MOS transistors T1 and T2 which are connected in series, the gates G1 and G2 of which are connected to each other and to an input node by way of capacitors C1 and C2. The gate of T1 is connected to its drain by a switch means S1. The input node is connected to an input terminal and a reference voltage terminal by switch means S4 and S3 respectively and an output node between T1 and T2 is connected to an output terminal by switch means S5. The gate of T2 is connected by way of a switch means S2 to a bias voltage source. The switch means S1 to S5 are actuated in such a way that in a first, preparation phase of the amplifier, switches S1, S2 and S3 are closed with the input node being at a reference voltage Vref and the currents I1 and I2 through T1 and T2 being equal to a value fixed by the voltage source and, in an amplification phase, switches S4 and S5 are closed so that the output current Is increases in absolute value with the voltage Ve applied to the input node.
Inventors:
ERIKU A UITOTSUTSU
Application Number:
JP4646182A
Publication Date:
February 09, 1990
Filing Date:
March 25, 1982
Export Citation:
Assignee:
SANTORU EREKUTORONIKU ORUROJE SA
International Classes:
H03F3/16; H03F3/00; H03F3/18; H03F3/20; H03F3/30; H03F3/34; H03F3/345; H03H19/00