Document Type and Number:
Japanese Patent JPH0320932
Kind Code:
B2
Abstract:
PURPOSE:To generate a cyclic code of an optional bit length by initializing an address counter and quickening the timing of a load based on each detection value of an address counter value of a memory and a serial output data value. CONSTITUTION:An n-bit data is loaded to a P/S converter 1 from a memory 2, and an n-bit data is transmitted serially one by one bit at the n-period of the clock. In this case, the arrival of the address counter 3 of the memory 2 to a prescribed value is detected by a comparator 6 and the arrival of the serial data to a prescribed location in an n-bit is detected by a comparator circuit 8. When the comparator circuits 6, 8 are operated at the same time, the counter3 is initialized to quicken the timing of a load to the conveter 1. As a result, the cyclic code of an optional bit length is generated with simple constitution.
Inventors:
YOSHIDA TADAHIRO
Application Number:
JP14519784A
Publication Date:
March 20, 1991
Filing Date:
July 11, 1984
Export Citation:
Assignee:
NITSUKO LTD
International Classes:
H03M13/00; G06F5/00; G06F11/10; H03K3/78; H03K3/84; H03M9/00
Next Patent: JPH0320933