Document Type and Number:
Japanese Patent JPH0373176
Kind Code:
B2
Abstract:
A clock generator circuit of this invention is for an integrated circuit which is controlled by clock signals obtained by frequency-dividing a standard clock. Three flip-flops, two of which are connected in series, and two logical gates together form a synchronization circuit such that when a command signal is inputted to start testing the integrated circuit, frequency-divided clock signals in synchronism with a standard clock are outputted.
Inventors:
HIRANO TAKAAKI
Application Number:
JP2739685A
Publication Date:
November 21, 1991
Filing Date:
February 13, 1985
Export Citation:
Assignee:
SHARP KK
International Classes:
H03K21/40; G01R31/28; H03K5/00; H03K5/135; H03K23/00; H03K23/40