Japanese Patent JPH0377690

B2

PURPOSE:To remove the limit of the maximum operating frequency of the circuit, by picking up the feedback signal from before n bits so that the delay time of the feedback can be neglected and making feedback with a delay, in a binary sequence circuit in which a plurality of FF circuits are in cascade connection. CONSTITUTION:FF circuits FF11-F13 are in cascade connection, the feedback signal is picked up from the output of FF11 and FF12 and it is fed to the delay line DL1 from the OR gate circuit G12, and delay is given by Td1 corresponding to one- bit's share and feedback input is made to the 1st stage FF11 of FF circuit. In comparison with the case that both the outputs of FF2, FF3 in FF circuit are fed directly back to FF1 conventionally, the delay time at the feedback circuit can be neglected by the feedback point before one bit, and high-speed operation can be made up to the toggle frequency of FF circuit.

WO/2019/030667	RANDOM NUMBER GENERATOR
JPH0936711	SCRAMBLE SIGNAL GENERATING CIRCUIT
JP2005159808	ANALOG-TO-DIGITAL CONVERTER

TODA YOSHIFUMI
MORITA TOSHUKI
ITO HIDEAKI
HODOHARA KYOAKI

JP3267080A

December 11, 1991

March 17, 1980

Click for automatic bibliography generation  

FUJITSU LTD

H03K3/84; H03K23/54

Next Patent: TREATMENT OF WASTE WATER